PCI-SIG drafts PCIe 7.0 spec with aim to finalize it in 2025

The group responsible for developing and updating the PCI Express standard, the PCI-SIG, aims to update that standard roughly every three years. Intel's latest 12th-generation Alder Lake processors include a limited number of PCIe 5.0 lanes, and PCIe 5.0 will also be part of AMD's Ryzen 7000 series later this year. Like all new PCI Express versions, its goal is to double the available bandwidth of its predecessor, which in PCIe 7.0's case means that a single PCIe 7.0 lane will be able to transmit at speeds of up to 32GB per second. A single PCIe 4.0 lane provides bandwidth of about 4GB per second, and you need eight of those lanes to offer the same speeds as a single PCIe 7.0 lane. As with all prior versions of the PCIe standard, the PCI-SIG says that PCIe 7.0 devices will remain fully backward compatible with older PCIe versions. It will be a year or two before we begin to see PCI Express 6.0 in consumer PCs, to say nothing of version 7.0. Most new standards take years to go from "draft" to "finalized" to "available in shipping products" to "ubiquitous," and new PCI Express versions are no exception. Version 6.0 was released earlier this year, and the group has announced that PCIe version 7.0 is currently on track to be finalized sometime in 2025. (Ars Technica). Continue reading.



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